In a display device such as an image display device, a data signal line drive circuit and a scanning signal line drive circuit are provided in order to drive a plurality of pixels, so that the pixels generate an image. Conventionally, in the data signal line drive circuit and the scanning signal line drive circuit, shift registers have been widely used for determining the timing when an inputted image signal is sampled, or for generating a scanning signal to be inputted to each of scanning signal lines.
As this type of shift register, the present applicant proposed an arrangement of a circuit shown in FIG. 9 (Document 1).
As illustrated in FIG. 9, in each stage of a shift resister 101, a set-reset type flip-flop 102 (“SR-FF” in FIG. 9) and an analog switch 103 are provided. To the shift register 101, a start pulse SSP and two clock signals SCK and SCKB whose phases are different from each other are inputted.
When a set signal inputted to an S terminal becomes active, the set-reset type flip-flop (hereinafter referred to as flip-flop) 102 is set, so that an output signal Q (Q1, Q2, . . . ) from a Q terminal becomes High (High level). Even when the set signal becomes inactive, this state of the output is maintained. When a reset signal inputted to an R terminal becomes active, the flip-flop 102 is reset, so that the output signal Q becomes Low (Low level). Even when the reset signal becomes inactive, this state of the output is maintained until when the set signal becomes active again.
In the flip-flops 102, the start pulse SSP is inputted as the set signal to a flip-flop 102-1 in a first stage placed at the leftmost of FIG. 9. To each of the flip-flops 102 in and after a second stage, an output signal X (X1, X2, . . . ) is inputted as the set signal, the output signal X (X1, X2, . . . ) outputted from an analog switch 103 corresponding to the flip-flop in a stage before a stage of the flip-flop 102 to which the output signal X (X1, X2, . . . ) is inputted. Moreover, to each of the flip-flops 102, an output signal X (X2, X3, . . . ) is inputted as the reset signal, the output signal X (X2, X3, . . . ) outputted from an analog switch 103 corresponding to the flip-flop in a stage after a stage of the flip-flop 102 to which the output signal X (X2, X3, . . . ) is inputted.
Each of the analog switches 103 is in an ON state while a corresponding flip-flop 102 is outputting an output signal Q (Q1, Q2, . . . ), and the analog switch 103 outputs the clock signal SCK or the clock signal SCKB as the output signal X (X1, X2, . . . ). The output signal X (X1, X2, . . . ) is outputted as an output signal of the shift register. Specifically, each of the analog switches 103 corresponding to the flip-flops 102 in odd stages outputs the clock signal SCK, and each of the analog switches 103 corresponding to the flip-flops 102 in even stages outputs the clock signal SCKB.
Note that, an inverter 104 in each of the analog switches 103 is provided for supplying control signals, which are opposite to each other, to gates of a PMOS transistor and a NMOS transistor which compose the analog switch 103 and are provided in parallel.
As described above, the clock signal SCK or the clock signal SCKB, both of which are the output signals X, is inputted to the flip-flop 102 in a following stage (a stage after a stage from which the output signal X is outputted) as the set signal. Meanwhile, the clock signal SCK or the clock signal SCKB is also inputted to the flip-flop 102 in a preceding stage (a stage before a stage from which the output signal X is outputted) as the reset signal.
In the above-described arrangement, the start pulse SSP is inputted as the set signal to the flip-flop 102-1 in the first stage, so that the flip-flop 102-1 is set. Then, the output signal Q1 becomes High.
The output signal Q1 from the flip-flop 102-1 becomes High, so that an analog switch 103-1 corresponding to the flip-flop 102-1 in the first stage becomes ON. Then, the clock signal SCK is outputted from the analog switch 103-1, as the output signal X1. The output signal X1 is outputted as an output signal from the first stage of the shift register 101.
Moreover, the output X1, which is the clock signal SCK, is inputted to a flip-flop 102-2 in a second stage as the set signal, so that the flip-flop 102-2 in the second stage is set. As in the above case, an output signal Q2 becomes High. The output signal Q2 from the flip-flop 102-2 in the second stage becomes High, so that an analog switch 103-2 corresponding to the flip-flop 102-2 in the second stage becomes ON. Then, the clock signal SCKB is outputted from the analog switch 103-2 as the output signal X2. The output signal X2 is outputted as an output signal from the second stage of the shift register 101.
As in the above case, the output signal X2, which is the clock signal SCKB, is inputted to a flip-flop 102-3 in a third stage as the set signal, so that the flip-flop 102-3 in the third stage is set. As a result, an output signal Q3 becomes High. Moreover, the output signal X2, which is the clock signal SCKB, is also inputted as the reset signal to the flip-flop 102-1 in the preceding stage, that is, in the first stage. Therefore, the flip-flop 102-1 in the first stage is reset, and the output signal Q1 becomes Low, and the analog switch 103-1 corresponding to the flip-flop 102-1 in the first stage becomes OFF.
In the stages of the shift register 101, a set-reset operation of the flip flops 102 and an ON/OFF operation of the analog switches 103 are successively carried out, so that the shift register 101 outputs the output signals X (X1, X2, . . . ), each of which has the same width as the width of the clock signal SCK or SCKB, and which do not overlap with each other.
Moreover, Document 2 describes a clock signal phase difference correction circuit provided in a stage before a stage in which a data line drive circuit or a scanning line drive circuit is provided. The clock signal phase difference correction circuit can surely remove phase difference between a clock signal and an antiphase clock signal which are inputted to the data line drive circuit and the scanning line drive circuit. Moreover, with the clock signal phase difference correction circuit, it is not necessary to increase a layout area of the drive circuit.
(Document 1)
Japanese Unexamined Patent Publication No. 135093/2001 (Tokukai 2001-135093, published on May 18, 2001, Corresponding U.S. Pat. No. 6,724,361 B1, Date of patent: Apr. 20, 2004)
(Document 2)
Japanese Unexamined Patent Publication No. 282397/1999 (Tokukaihei 11-282397, published on Oct. 15, 1999)
However, according to an arrangement of the above-described conventional shift register 101, there is a problem that the shift register 101 may malfunction when the clock signals SCK and SCKB are out of phase.
The following description explains this malfunction in reference to FIG. 10. FIG. 10 is a timing diagram illustrating each operation of the shift register 101. In FIG. 10, the clock signals SCK and SCKB are out of phase. The phase of the clock signal SCKB is shifted from the phase of the clock signal SCK in a retardation direction.
The flip-flop 102-1 in the first stage is set at a rise (A) of the start pulse SSP, so that the output signal Q1 becomes High. While the output signal Q1 is High, the analog switch 103-1 corresponding to the flip-flop 102-1 in the first stage is ON, so that the clock signal SCK is outputted as the output signal X1. Then, the output signal X1 is inputted as the set signal to the flip-flop 102-2 in the second stage, so that the flip-flop 102-2 in the second stage is set at a rise (B) of the output signal X1. As a result, the output signal Q2 becomes High.
However, the phase of the clock signal SCKB is shifted from the phase of the clock signal SCK, so that there is a period when both the clock signals SCK and SCKB are High. Therefore, an unnecessary pulse PP, which corresponds to a delay (lag) of the clock signal SCKB and is illustrated by hatched lines in FIG. 10, is outputted as the output signal X2 before an original pulse PPP of the clock signal SCKB is outputted. The output signal X2 is the set signal of the flip-flop 102-3 in the third stage. Therefore, although the flip-flop 102-3 in the third stage should be set at the time of (D), it is set at the time of (C) because of the unnecessary output signal X2.
As a result, an analog switch 103-3 corresponding to the flip-flop 102-3 in the third stage outputs an output signal X3 at the time when the output signal X1 is outputted. Therefore, all the flip-flops in and after the third stage are set at the same time. As a result, the shift register 101 does not function properly, so as to malfunction.
Moreover, the phase difference between the clock signals SCK and SCKB is also generated while the clock signals SCK and SCKB are transmitting inside the shift register 101. Therefore, even in cases where the clock signal phase difference correction circuit described in Document 2 is provided at a signal input side of the shift register 101, it can only deal with the phase difference of the signals before inputted to the shift register 101. In cases where the phase difference between the clock signals SCK and SCKB is generated inside the shift register 101, the shift register 101 malfunctions after all.